TSMC 3nm will conduct trial production as planned: the speed will be increased by 11% and energy saving by 27%

TSMC is continuously promoting the diversified applications of 3nm development. According to the data, the target of the process node is more advanced in efficiency, power consumption and area (PPA) than that of the 5nm family, which will save energy by 27% when the speed is increased by 11%. In addition, there are several versions of the 3nm family that are extended to meet the needs of HPC customers.
TSMC recently released more data on the evolution process of advanced process technology in the open innovation forum. According to the briefing of the forum organized according to semiwiki, the advanced process of TSMC continues to advance. If the arm architecture is simulated, the target PPA of 3nm process will be achieved under the design technology collaborative optimization (DTCO) of open innovation partners, including an increase in logic density compared with 5nm! More than 1.6 times, transmission speed increased by 11% and energy saving by 27%.
At the same time, TSMC also demonstrated n3hpc related technologies of 3nm family on the forum.
Previously, foreign investors in the US Department warned that TSMC's 3nm process encountered technical problems and may be postponed to the trial production in the first half of next year, one to two quarters later than the original schedule.
In this regard, Wei Zhejia, President of TSMC, said at the French speaking meeting on October 14 that TSMC 3nm was developed according to the plan, with the participation of many customers, and has also developed a complete platform to support high-performance computing and smart phone applications. The target is trial production in 2021, and mass production is expected in the second half of 2022.
Wei Zhejia also announced that TSMC will launch n3e process, which will be introduced into mass production one year after the mass production of 3nm process. It means that the n3e process will be mass produced in the second half of 2023.
Wei Zhejia also revealed that the 2nm process will adopt the surround gate (GAA) architecture, which is expected to be mass produced in 2025. This is the first time TSMC has revealed the technological process of 2nm process. Wei Zhejia would not comment on competitors, but he stressed that TSMC's 2nm process technology will be the most competitive in density and efficiency.

Commax-Tech Electronic Co., Ltd      Electronic component specialist

B23, second floor, ASEAN building, Longhua District, Shenzhen

sales@commax-tech.com

https://commax-tech.com

Keyword：TSMC 3nm   Efficiency   Power Consumption   Area   Design Technology Collaborative Optimization   Transmission Speed Improvement   N3HPC   High Performance Computing   Smart Phone Application   Ground Gate (GAA) Architecture   Commax-Tech Electronic